1. Field of the Invention
The present invention relates to a process for translating a header of a cell applied to the input of a node of an asynchronous packet data transmission network.
It applies in particular to the digital data switching and cross-connection equipment making up a network operating in the mode of transmission known by the abbreviation ATM standing for xe2x80x9cAsynchronous Transfer Modexe2x80x9d.
2. Discussion of the Background
The ATM asynchronous transfer mode is mainly defined in the recommendations of the ITU-T (series I), as well as in the work of an industrial grouping dubbed the xe2x80x9cATM Forumxe2x80x9d.
In the ATM asynchronous transfer mode the information to be transmitted is grouped together in the form of packets. Together, header plus data is dubbed a cell. Basically, ATM operates in a connected mode, that is to say it has to establish a route through the transmission network before being able to transmit the data. This route is termed a xe2x80x9cvirtual circuitxe2x80x9d. There are in general numerous virtual circuits which follow the same physical connection between two items of ATM equipment. The main role of the header of the cells is to allow the identification of the virtual circuits over the link. An example of implementing such a process is known in particular from French Patent Application No. 2 681 164 filed in the name of the Applicant.
A virtual circuit is obtained by placing end-to-end virtual communication pathways established between adjacent switches. These pathways are of two types: virtual paths or virtual channels, the virtual channels being regarded as a subdivision of the virtual paths. On a given highway, any virtual circuit is fully determined by indicating the identifier of the virtual path (VPI) and that of the virtual channel (VCI) which it follows, in the case of a circuit to be switched in VC mode (VCC), or else by indicating just the identifier of the virtual path (VPI), in the case of a circuit to be switched in VP mode (VPC).
According to this process, each cell to be routed within a network is composed on the one hand of a header making it possible to identify it and guide it through the pathways making up the virtual circuit, and on the other hand, of a part containing the information to be conveyed. Routing is effected at the level of each node of the network by extracting from the header the address of a word contained in a first context memory containing the information required for identifying the header and for guiding the data to be conveyed and by creating a new address on the basis of the word read from the first context memory. This new address serves as a pointer to an area of a second context memory in which there is at least one new header and one outgoing direction information cue for the cell or cells exiting the node.
The translation function which is thus carried out makes it possible for each cell to be associated with the information enabling it to undergo the processing operations for which it is intended. The translator which is responsible for executing this function on each cell which it receives must typically provide information about the validity of the virtual path identifier, the validity of the virtual channel identifier, counting, the list of outgoing directions in which the cell received is transmitted, the new header associated with the cell during its transmission etc. The translator must also execute the processing operations corresponding to the context defined previously for each cell. These processing operations relate in particular to virtual path (VP) switching, virtual channel (VC) switching and the extracting of the maintenance flows.
From the structural standpoint the translation function is carried out with the aid of a memory plane addressed by a microprogrammed processing unit.
However, this very large memory plane, whose size may contain for example 232 words of 16 bits, is difficult to manage.
To alleviate this difficulty, the French Patent Application published under No. 2 726 669 filed by the applicant proposed that the memory space of the node be addressed on the basis of the virtual path number VPI contained in the header of the cell so as to identify in this space a first context area indicating the range of the virtual channels which can be used by the cell for this VPI
and that a second context area be addressed on the basis of a virtual channel number VCI contained in the header of the cell and of a base address read from the first context area so as to obtain the list of directions which the cell must take on exiting the node, as well as the new header.
However, this process proves to be poorly suited to the constraints imposed by the new virtual interfaces of switches such as for example the xe2x80x9cVirtual UNIxe2x80x9d interface specified in chapter A7-4 of the ATM Forum""s xe2x80x9cUNI signalling version 4.0xe2x80x9d specification. It does not for example allow a rearrangement of the translation memory when there is a modification in the number of users who, on one and the same physical interface, are sharing the virtual path capacities.
This is manifested through the appearance of gaps in the translation memory which limit the possibilities for utilizing the whole spectrum of possible VPI and VCI values.
The purpose of the invention is to alleviate the abovementioned drawbacks.
To this end, the subject of the invention is a process for translating an ATM cell header for the routing thereof on a transmission highway of a communication network via an ATM switch, the header of the cell comprising a first field VPI and a second field VCI, the first field VPI identifying a virtual path number and the second field VCI selecting a specified virtual channel within the virtual path, characterized in that it consists:
in storing indirect addressing context page numbers in a first major table,
in storing context page numbers for the circuits in VP switching mode in a second major table,
in storing context page numbers for the circuits in VC switching mode indirect addressing context pages,
in addressing the context pages of circuits in VC switching mode by way of an indirect addressing context page of the context page numbers on the basis of the first major table and of the second field VCI, and
in addressing the context pages of the circuits in VP switching mode on the basis of context page numbers contained in the second major table.
The main advantage of the invention is that it associates the N contexts determined by the available memory size with a number of connections of the same order of magnitude as N, even if the identifiers (VPI, VCI) of its connections describe ranges of values which are multiples from among the 228 theoretically possible values. It also allows partial modifications of the configuration of a network consisting for example in modifying a VP switching mode into a VC mode for a specified VPI value or else in activating/deactivating a consequent string of VPI values, without impairing the operational functioning involving the VPI and VCI values for which the modification is not relevant. As another advantage the size of the translation memory is suited to the strict need of a limited number of connections (either VPC or VCC), this number being small relative to the numbers of possible combinations of the VPI/VCI values. On the other hand, the translation operations, especially those giving rise to slow memory accesses, are reduced to a minimum number, thereby making it possible to process ATM flows with high bit rates of for example greater than 155 Mbps. Finally, it allows the installation of a temporary bypass to a built-in test probe in VP switching mode so as to observe the traffic over certain virtual channels VC.